Electronics · Digital logic and control / Principles and inquiry
ADC sampling and quantization experiment guide
Separate sampling and quantization errors and check whether slow sampling reveals a different frequency.
How does it work?
Aliasing occurs below twice the signal frequency, while more bits reduce quantization steps.
Key relationship
Δ = 4/(2ⁿ−1) · falias = |f−round(f/fs)fs|
Try this investigation
- Separate sampling and quantization errors and check whether slow sampling reveals a different frequency.
- Run and record each of the three baseline presets.
- Compare the changed variable and its result with the baseline records.
Interpreting your results
What is the step size for 4-bit quantization from −2 V to +2 V including both endpoints?
About 0.267 V
Assumptions and limitations
Noise, jitter and real ADC nonlinearities are omitted. The fs=2f boundary is phase-sensitive and is not marked safe. Experiment on screen; do not reproduce this with real power supplies, outlets or high voltage.