Meaning and mechanism
A half adder adds two input bits, while a full adder adds three inputs, including the carry from the preceding position. Connecting the results across positions allows multi-bit addition.
Using XOR with respect to an odd number of 1, addition can be expressed as carry when there are two or more 1 in the input. If all three inputs are 1, the addition results in 1 and the carry is 1.
Relationships and conditions
S=A⊕B⊕Cin and Cout=AB+Cin(A⊕B). The number must include the final carry bit to equal the complete sum A+B+Cin.
If we drop the carry in the fixed bit count, the number will cycle. The detection of overflow for both sign carry and unsigned numbers is not the same concept.
What to observe in the simulation
The sum bits together with the final carry equal A+B+Cin.
Propagation delay and intermediate voltages are omitted. Inputs are integers from 0 to 15. Experiment on screen; do not reproduce this with real power supplies, outlets or high voltage.
Key relationships and symbols
S = A⊕B⊕Cin · Cout = AB + Cin(A⊕B)
| Symbol | Meaning | Unit |
|---|---|---|
| S | Sum bit at the current position | 0 or 1 |
| Cin, Cout | Carry-in and carry-out | 0 or 1 |
Worked example
With A=15, B=15 and Cin=1, what are the final carry and sum bits?
1 / 1111
Common misconceptions
- Reading only an adder’s output bit while ignoring the carry can miss the actual sum.